In order to realize a very large-scale integrated circuit (VLSI) having even higher integration, the size of a MOS type semiconductor device usable for such a VLSI has been reduced more and more in recent years. As a result, currently available devices are formed with a minimum size in a half-micron region or in a sub-half micron region. However, if a device having such a fine size is formed, the electric characteristics of such a device are likely to be degraded because of a short-channel effect or a hot-carrier effect, thereby seriously influencing the reliability of the device.
On the other hand, in order to develop VLSI technologies satisfactorily applicable in the expanding multi-media society, a semiconductor device must realize not only high-speed operation but also low power consumption.
In order to improve the resistance of a device to the degradation caused by a hot-carrier effect or a short-channel effect and to improve the drivability thereof, a MOS type semiconductor device having an asymmetric impurity profile in the channel has been suggested. Such a MOS semiconductor device is described, for example, by T. Matsui et al. in 1991 Symposium on VLSI Technology, pp. 113-114, in which a laterally-doped channel (LDC) structure is disclosed.
FIG. 14 is a cross-sectional view showing a MOS type semiconductor device having an LCD structure.
The semiconductor device includes: an n-type high-concentration source diffusion layer 2 and an n-type high-concentration drain diffusion layer 3 which are formed in a semiconductor substrate 1; a gate oxide film 4 formed on the semiconductor substrate 1; a gate electrode 5 formed on the gate oxide film 4; and a p-type high-concentration diffusion layer 6' provided in a channel region between the source diffusion layer 2 and the drain diffusion layer 3 and under the source diffusion layer 2 in the semiconductor substrate 1. The p-type diffusion layer 6' is characterized in that the impurity concentration thereof monotonically decreases from the source side to the drain side. In this structure, by setting the impurity concentration on the source side of the p-type diffusion layer 6' to be high, it is possible to improve the resistance of the device to the short-channel effect. In addition, by setting the impurity concentration on the drain side of the p-type diffusion layer 6' to be low, it is possible to reduce a high electric field generated in the vicinity of the drain, thereby suppressing the generation of hot carriers. Therefore, a conventional lightly-doped drain (LDD) structure is not required for this semiconductor device, thereby realizing high drivability.
However, this structure is not suitable for a MOS type semiconductor device to be formed in a region having a size on the order of a quarter micron or less. This is because, the MOS type semiconductor device having the LDC structure shown in FIG. 14 has the following problems.
(1) A p-type high-concentration diffusion layer is provided under a source diffusion layer and the impurity concentration in the p-type diffusion layer is as high as 1.times.10.sup.18 cm.sup.-3 or more in order to suppress the short-channel effect. As a result, the parasitic capacitance of the p-n junction between the source and the substrate is adversely increased as compared with a conventional structure. In general, the speed of a VOS type semiconductor device is proportional to the product obtained by multiplying together an inverse of a saturated current value and a load capacitance. Therefore, if such a semiconductor device having a large parasitic capacitance in the p-n junction between the source and the substrate, as in the case of a semiconductor device having a LDC structure, is applied to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is adversely decreased. On the other hand, the power consumed by a MOS type semiconductor device is proportional to the product obtained by multiplying together the load capacitance and the square of the applied voltage. Therefore, the power consumption of the circuit is adversely increased.
(2) The p-type diffusion layer for controlling the threshold voltage and suppressing the short-channel effect reaches the surface of the substrate and the impurity concentration on the source side of the channel region is as high as 1.times.10.sup.18 cm.sup.-3 in the vicinity of the surface of the substrate. As a result, the mobility of the carriers is considerably decreased on the source side because of the scattering of the impurity. Since the current value of a MOS type semiconductor device is determined by the behavior of the carriers on the source side, the saturated current value is decreased.
(3) When a device having a size on the order of a quarter micron or less is formed, the threshold voltage is decreased and the device becomes seriously affected by the short-channel effect. The short-channel effect depends upon an effective channel length and a junction depth between the source diffusion layer and the drain diffusion layer. Since a LDC structure has a deep junction depth between the source diffusion layer and the drain diffusion layer, the decrease in the threshold voltage cannot be suppressed in a region having a size on the order of a quarter micron or less.
(4) In fabricating a semiconductor device having a LDC structure, an additional process step of masking the drain electrode is necessary when a p-type diffusion layer is formed on the source side.
Because of the above-described reasons, a highly reliable high-speed semiconductor device cannot be formed in a region having a size on the order of a quarter micron or less according to the conventional technologies for forming a MOS type semiconductor device.